RTL Design Engineer
Role and Responsibilities
- Experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem.
- Understanding of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.
- Creating micro-architecture and detailed design documents for SoC Subsystem design keeping in mind performance, power, area requirements.
- Strong debugging skills and very good experience in DV tools like Verdi, NCSIM.
- SOC Integration experience preferred of Top Level, Block Level or Subsystem level.
- Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modelling team.
- Must have knowledge in clock domain crossing (CDC), Linting, UPF, DFT and Multi-Voltage-Rule-Check analysis.
- Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc. is a must.
- Understanding and defining constraints and critical high speed path timing closure working with back end teams.